1. Field of the Invention
The present invention relates generally to a method for manufacturing a plurality of passive elements in a semiconductor integrated circuit, and more particularly to a method for manufacturing a metal-insulator-metal capacitative element and a thin metal film resistive element in the same process in a semiconductor integrated circuit. Also, the present invention relates to a semiconductor integrated circuit in which the passive elements manufactured according to the method are arranged.
2. Description of the Related Art
In a semiconductor integrated circuit, various types of passive elements such as a capacitative element and a resistive element are integrated. The capacitative element such as a metal-insulator-metal capacitative element is generally manufactured by laminating a first metal layer, an insulating film, and a second metal layer in that order.
2.1. First Prior Art
For example, the insulating film consists conventionally of Silicon Nitride (SiN) in a compound semiconductor integrated circuit. In this case, a relative dielectric constant .epsilon.r of SiN is no more than 7.2. Therefore, a large area is required to manufacture a capacitative element having a capacity C=S*.epsilon.r/d such as a several tens pF value (the symbol S denotes an area of the capacitative element and the symbol d denotes a film thickness of the insulating film). As a result, an area occupied by a semiconductor integrated circuit is increased, and a manufacturing cost of the semiconductor integrated circuit is increased.
To solve the above drawbacks, the application of an insulating material having a comparatively high relative dielectric constant .epsilon.r to the capacitative element has been recently proposed. For example, a tantalum oxide film of which a relative dielectric constant .epsilon.r ranges from 22 to 25 has been proposed (Japanese Patent Application No. 113218 of 1983 laid open to public inspection on Jan. 12, 1985 under Provisional Publication No. 5555/85). However, in cases where the tantalum oxide film is utilized as the insulating film of the metal-insulator-metal capacitative element in place of a SiN film, leakage current flowing between the first and second metal layers through the tantalum oxide film is increased as compared with that in the SiN film. Therefore, the film thickness of the tantalum oxide film is required to be twice or three times as thick as that of the SiN film. As a result, an area S.sub.Ta occupied by the capacitative element in which the tantalum oxide film is laminated is the same as another area S.sub.SiN occupied by the capacitative element in which the SiN film is laminated.
To solve the above drawback, the application of an insulating film consisting of titanium oxide (Ti-oxide) to the capacitative element has been recently proposed. A relative dielectric constant .epsilon.r of Ti-oxide is generally larger than that of Ta-oxide such as tantalum oxide because a relative displacement of a titanium atom to an oxygen atom in a perovskite structure is greatly larger than that of a tantalum atom to an oxygen atom. That is, a dipole moment in Ti-oxide is larger than that in Ta-oxide. Specifically, in cases where SrTiO.sub.3 is utilized as a Ti-oxide insulating film, a relative dielectric constant .epsilon.r of SrTiO.sub.3 ranges from 100 to 300. In other words, the relative dielectric constant .epsilon.r of SrTiO.sub.3 is fourteen times to forty-two times as large as that of SiN. Also, leakage current flowing through a SrTiO.sub.3 film is easily suppressed by increasing the film thickness of the SrTiO.sub.3 film. That is, an increased film thickness of the SrTiO.sub.3 film is no more than four times as large as the film thickness of the SiN film to decrease density of the leakage current to 10.sup.-6 A/cm.sup.2 or below. As a result, an area S.sub.Ti occupied by the capacitative element in which the SrTiO.sub.3 film is laminated is decreased to a range from 1/3.5 to 1/10.5 as compared with the area S.sub.SiN.
Accordingly, the reduction of the area occupied by the capacitative element can be achieved. In addition, Curie temperature of SrTiO.sub.3 is about 75.degree. K. and is considerably low. Therefore, a polarization reversal is not observed in SrTiO.sub.3 in cases where the capacitative element is operated at an ordinary temperature. Accordingly, the application of the SrTiO.sub.3 film to the capacitative element is proper for a circuit in which signals are transferred in a high-frequency band such as a band over 1 GHz.
The selection of a material of the insulating film is described as a first prior art in the above description.
2.2 Second Prior Art
Next, a second prior art is described.
In cases where a plurality of passive elements are arranged in a semiconductor integrated circuit, not only a capacitative element but also a resistive element are generally arranged on a substrate.
FIGS. 1A to 1J are sectional views showing a series of conventional processes for manufacturing a capacitative element and a resistive element on a substrate.
In cases where a capacitative element and a resistive element are manufactured on a layer insulation film 11 deposited on a substrate 12, a first metal film 13 is initially deposited over the entire layer insulation film 11 in a first process as shown in FIG. 1A. Thereafter, the first metal film 13 is etched to a prescribed pattern to form a first metal layer 13a according to a photolithography technique in a second process as shown in FIG. 1B. Thereafter, an insulating film 14 is deposited over entire surfaces of the first metal layer 13a and the layer insulation film 11 in a third process as shown in FIG. 1C. Thereafter, the insulating film 14 is etched to a prescribed pattern to form an insulating film 14a on the first metal layer 13a in a fourth process as shown in FIG. 1D. Thereafter, a second metal film 15 is deposited over entire surfaces of the insulating film 14a, the first metal layer 13a and the layer insulation film 11 in a fifth process as shown in FIG. 1E. Thereafter, the second metal film 15 is etched to a prescribed pattern to form a second metal layer 15 a on the insulating film 14a in a sixth process as shown in FIG. 1F. Therefore, a capacitative element 16 consisting of the first metal layer 13a, the insulating film 14a, and the second metal layer 15a is formed.
Thereafter, a thin metal film 17 is deposited over entire surfaces of the second metal layer 15a, the first metal layer 13a and the layer insulation film 11 in a seventh process as shown in FIG. 1G. Thereafter, the thin metal film 17 is etched to a prescribed pattern to form a thin metal film resistor 17a on the layer insulating film 11 in an eighth process as shown in FIG. 1H. The thin metal film resistor 17a functions as the resistive element. Thereafter, a passivation film 18 is deposited over entire surfaces of the second metal layer 15a, the first metal layer 13a, the layer insulation film 11, and the thin metal film resistor 17a in a ninth process as shown in FIG. 1I. Finally, the passivation film 18 is etched to make a plurality of via holes 19 through which each of wires is connected with the second metal layer 15a, the first metal layer 13a, or the thin metal film resistor 17a in a tenth process as shown in FIG. 1J.
Therefore, the seventh and eighth processes are additionally required to arrange the thin metal film resistor 17a in cases where the capacitative element 16 and the thin metal film resistor 17a are independently deposited on the substrate 12.
2.3. Problems to be Solved by the Invention
However, there are many drawbacks in the first prior art. That is, when heat treatment is performed for the capacitative element after the first metal layer, the SrTiO.sub.3 film, and the second metal layer are deposited in that order, thermal reaction is generated between the SrTiO.sub.3 film and the second metal layer. As a result, leakage current between the first and second metal films through the SrTiO.sub.3 film is remarkably increased.
FIG. 2A is a sectional view of a conventional capacitative element manufactured on a semiconductor chip. FIG. 2B is an enlarged sectional view showing dislocation of oxygen atoms from a SrTiO.sub.3 thin film to a second metal layer in the conventional capacitative element shown in FIG. 2A.
As shown in FIGS. 2A, 2B, a conventional capacitative element 21 consists of a first metal layer 22 deposited on a substrate 23, a SrTiO.sub.3 thin film 24 deposited on the first metal layer 22, and a second metal layer 25 deposited on the SrTiO.sub.3 thin film 24. The second metal layer 25 consists of a metal material such as Ti, Ni, or Al which is easily oxidized. In the above configuration, because the SrTiO.sub.3 thin film 24 functions as an insulating film, the conventional capacitative element 21 functions as a capacitor. When heat treatment is performed for the capacitative element 21 at a temperature of several hundreds degrees C after the capacitative element 21 is manufactured, oxygen ions 26 bonded to Sr ions or Ti ions in the SrTiO.sub.3 thin Film 24 are freed and diffused into the second metal layer 25 (W. B. Pennebaker, IBM Journal of Research and Development, 13, 686(1969)). Therefore, the second metal layer 25 is oxidized, and lattice defects 27 in which oxygen ions 26 are lost are generated. As a result, electrons are transferred from the first metal layer 22 (or the second metal layer 25) to the second metal layer 25 (or the first metal layer 22) through the lattice defects 27 of the SrTiO.sub.3 thin film 24.
FIG. 3 graphically shows a relationship between density Ic(A/cm.sup.2) of leakage current flowing through the SrTiO.sub.3 thin film 24 and intensity E(V/cm) of electric field applied to the capacitative element 21.
As shown in FIG. 3, leakage current flowing through the SrTiO.sub.3 thin film 24 is comparatively high even though intensity E(V/cm) of electric field applied to the capacitative element 21 is low. That is, density of the leakage current is more than 10.sup.-2 A/cm.sup.2 in cases where the lattice defects 27 are generated in the SrTiO.sub.3 thin film 24. The density of the leakage current is maintained at 10.sup.-6 A/cm.sup.2 or below in cases where any lattice defect 27 is not generated in the SrTiO.sub.3 thin film 24. Also, when the intensity E(V/cm) of the electric field is increased to 0.35 V/cm, a dielectric breakdown is generated in the capacitative element 21.
Accordingly, an insulating property of the capacitative element 21 deteriorates, and the capacitative element 21 cannot be useful for practical use.
To solve the above drawback, the application of nonreactive noble metals such as Au and Pt to the second metal layer 25 has been proposed. Because the noble metals Au and Pt are non-reactive, the oxygen ions 26 bonded in the SrTiO.sub.3 thin film 24 are not diffused into the second metal layer 25 consisting of Au or Pt. However, adhesion of the noble metals to the insulating film 24 is low. Therefore, in cases where a passivation film is deposited on the capacitative element 21, a so-called membrane stress is generated between the passivation film and the second metal layer consisting of Au or Pt after a while. As a result, the second metal layer 25 comes off the SrTiO.sub.3 thin film 24 so that yield rate of the semiconductor integrated circuits deteriorates. Also, crevices penetrating the passivation film and the second metal layer 25 are produced so that an insulation property of the capacitative element 21 is varied by a moist atmosphere. In addition, in cases where ultrasonic cleaning is performed for the capacitative element 21, the second metal layer 25 comes off the SrTiO.sub.3 thin film 24 because the adhesion of the noble metals to the insulating film 24 is low.
Also, to decrease the number of processes in the second prior art shown in FIGS. 1A to 1J, there is a first conventional method in which the thin metal film resistor 17a is deposited together with the second metal layer 15. In this case, the control of a film thickness of the thin metal film resistor 17a is required to adjust the resistance of the thin metal film resistor 17a. However, because sheet resistance .rho..sub.s (.OMEGA..quadrature.) of the noble metal such as Au or Pt is considerably low, the sheet resistance .rho..sub.s is, for example, less than 1 .OMEGA./.quadrature. on condition that the film thickness of the thin metal film resistor 17a is 50 nm. Therefore, the film thickness and a film width of the thin metal film resistor 17a is required to be controlled with high accuracy in cases where the thin metal film resistor 17a having a high resistance is required. Also, the resistance of the thin metal film resistor 17a has an upper limit. Accordingly, there are many drawbacks in the first conventional method as to the resistance control of the thin metal film resistor 17a and the reproductivity of the thin metal film resistor 17a in cases where the noble metal is deposited to simultaneously produce the thin metal film resistor 17a and the second metal layer 15a.
Also, there is a second conventional method in which the thin metal film resistor 17a is produced together with another metal layer (not shown) in a single process to decrease the number of processes shown in FIGS. 1A to 1J. For example, the thin metal film resistor 17a is deposited together with a gate electrode (Japanese Patent Application No. 34494 of 1987 laid open to public inspection on Aug. 22, 1988 under Provisional Publication No. 202951/88). However, because an annealing process is performed at an annealing temperature of about 800.degree. C. to activate injected ions after the thin metal film resistor 17a is deposited together with the gate electrode, nitrogen content of the thin metal film resistor 17a is considerably increased. Therefore, the resistance of the thin metal film resistor 17a is varied. Accordingly, the resistance of the thin metal film resistor 17a cannot be adjusted with high accuracy in the second conventional method.
Also, there is a third conventional method in which the thin metal film resistor is produced together with the first metal layer 13a in a single process. However, a surface of the thin metal film resistor 17a is damaged when the SrTiO.sub.3 thin film 14a is processed. Therefore, the resistance of the thin metal film resistor 17a is varied. Accordingly, the resistance of the thin metal film resistor 17a cannot be adjusted with high accuracy in the third conventional method.